• Introduction story
• Advanced characteristic of C64 and problems with construction of DDemon
• List of hardware and software that you need
• Electric scheme of interface between C64 and ISA card (picture from Electronic Work Bench)
• Download stuff

• C64 has 512 bytes of address space reserved for I/O devices similar to the PC I/O address space of 1024 bytes in which you can find control register of serial,parallel ports and other I/O devices within PC. This address space in C64 is decoded by two signals (I/O1 and I/O2 ) which are derived on the expansion port of C64
• C64 has DMA input making possible to stop operation of CPU and to take full control over data and address bus. You may say that C64 has already implement logic for DMA type of data transfer.

1. C64/128
2. 1.44Mb floppy-diskette unit for PC and cable for floppy
3. ISA card with FDD controller (you can get it from old PC's where FDD/HDD controller isn't integrated in motherboard)
4. Interface for DMA transfer: basically it's PCB (printed circuited board) with TTL elements as interface betwen C64 and ISA card (optionally EPROM).
5. ISA slot (can be also integrated/soldered on PCB)

1. C64 Disk Commander (shell that looks like Norton Commander) this is the emulation of PC-DOS on C64.
2. C64 Word this is common text editor for C64 which can store text in ASCII-format with ability to view files greater then 64Kb. Also it recognize USA,CRO i C64 character set. It can operate with 3.5inch diskettes and with cassettes.

This el. scheme looks complicated but this is due to real life digital circuits (such as 74139 and other). Logical scheme (created by simple parts such as NOT, JK and other parts) is much more understandable and simpler but I don't have time to make it.
I have never implemented EPROM module so signals such as CE,ROMH,ROML and EXROM/GAME were never used. Points (junctions) with same name are connected (e.g. CLOCK ).On scheme there are four types of signals:
INTERNAL - used only between elements on scheme (e.g. DEX2/$DFDO,CLOCK,LE,..)
C64 - connected only to the expansion port of C64 (e.g. IRQ/C64,RESET/C64,R/W,..)
AT-CARD - connected only to AT-CARD (e.g. RES/FDD,IRQ 6,DRQ 2,DACK 2,..)
SHARED - signals that are shared by C64,AT-card and this DMA interface and usually with three- state ability (e.g. data and address lines D0-D7, A0-A15)
IC 4040 has strange pin out (you can view it from EWB4 because it is custom made IC) but basically it has two controls inputs:
RESET-resets counter to zero; CLOCK - CLOCK is negative-edge sensitive input;
Two power pins: Vcc and GND
11 counter outputs (used as address lines).
For detailed description about signals on scheme you must download that zip file (at bottom of page).

DMA TRANSFER

4040 and 2*74244 are 11-bit (2048) counter with tri-state outputs. Purpose: to address C64 memory at DMA transfer (read or write).
CLOCK is negativ-edge sensitive input, CLEAR/4040 resets counter when is "1",DMA controls outputs of counter: when "0" then DMA transfer is active (address outputs of counter are connect to address bus of C64.
Function CLEAR/4040 is obtain by IRQ 6, interrupt caused by FDD.
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First JK bistabil is used for synchronization of FDD and C64. When DRQ 2 is active ("1") then it is needed at negative edge of FI2 (system clock of c64) to pull down DMA input of C64 at "0" which halts CPU and regain control over address & data bus of  C64 (which makes possible for direct read/write in C64 memory by bringing proper address which is provide by our 11-bit counter).

PROGRAMING DMA

8-bit latch 74373 is used to memorize other address signals (A12-A15), to fully decode 16-bit address of C64.
Also contains values for other signals:
R/W (for C64, to notify C64 type of operation: read from C64 memory or write in memory
R  W  (for FDD same purpose)
These values are written just one time before DMA cycles. Latch provides change of address at which the data is to be read from or written in memory of C64 at DMA transfer (in 2KB jumps)
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All these signals are active when DMA cycle is active (DMA ="0", DMA line is connected to OC input of latch (output enable))
To write data into latch it is needed to select it by demultiplexer 74139 with inverted signal DEX1. (LE).
When DEX1 is at "0" (C input of latch at "1" (LE=1)), then data on data bus is being written in latch.
Address of latch in C64: DFE0-DFEF.

ADDRESSING FDD REGISTERS

To access data stored on diskette it is needed to address FDD control registers:
registers are at $DFF0-$DFF7:
-with I/O1 and I/O2 the AEN signal is generated which selects all AT-card, then with address signals A0-A8 (generated by C64) it's possible to precise address FDD registers. That kind of access provides user to easly access FDD-control registers, GAME,COM1,COM2 and LPT port registers (by commands such are PEEK i POKE).
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Also you need to generate R and W signals for FDD: R/W from C64 is inverted and connected through 74244 which isn't used in counter.
(when R/W "1": R=0 ; W=1 and vice versa)
This is necessary because these signals are needed to be disconnected (in tri-state) when DMA-cycle is active. (AEN signal controls when these signals are in tri-state: AEN ="0": R i W are active)
(lines marked by blue to differ from counter connections)
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Note: it seems that R input of FDD has to be pulled up to power by resistor (3.3K) because when it is in tri-state it goes in "0" which causes errors.

INITIATION: signals CLEAR/JK,IRQ 6,DRQ 2

It is needed to assure that DMA-device dont turn himself on because of some reason, and to start to work from known states (JK-bistabiles).
If FDD doesn't work or if FDD registers are not initialized then IRQ 6 output from AT-card float at "1" same as DRQ 2 (signal IRQ 6 is actived at end of DMA cycle, until DRQ 2 is in non-stop use at DMA transfer).
That characteristics I have used in my schemes:
IRQ 6 signal from FDD is used as CLEAR/JK signal, when it is on "1" then he blocks JK- bistabil and clears counter (CLEAR/4040).
Also to obtain real function of IRQ 6 signal (to signalize end of DMA cycle) I have to gate it by DRQ 2 signal on IRQ line of C64 (IRQ 6 active at "1").
When DRQ 2 is at "0" then it is possible for IRQ 6 to set IRQ line of C64 at "0" ( at same time reseting counter and JK-bistabil).
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That signal have to be gated through log. devices of OC (open collector) or Thri-state ability, because IRQ line of C64 is pull-up and you cannot connect ordinary log. device to it.

EPROM (optional)

To address EPROM you need to decode CE signal by ROMH and ROML outputs from C64.
To plug in EPROM in address space of C64 you need to set lines EXROM/GAME at "0".
Second JK bistabil (T-type) is responsible for that. It's triggered by neg. edge of  DEX2 signal (at dfd0-dfdf) from demultipexer 74139.
That means that by addressing these locations you can "turn on or off" your EPROM from C64 address space.
The RESET line of C64 is connected to CLR input of bistabil which provides to turn on EPROM just at powering-up time of C64.